Data: Size of main memory: 16 MB Size of cache memory: 64 KB Block/line size: 256 B The cache memory has been designed as 4- way set associative. Calculation: The memory is Byte- addressable. Main memory size = 16 MB = 224 B. That means physical address generated by CPU would be represented using 24 bits. Cache memory size = 64 KB = 216 B Block size = 256 B = 28 B. i.e. word would be represented by 8 bits Therefore, Number of cache lines ÷ blocks = 216 ÷ 28 = 28 Since, the cache memory is 4-way set associative. Hence, number of sets = 28 ÷ 22 = 26. i.e. 6 bits would be required for set/index. Therefore, Number of bits for tag = 24 – (6 +8) = 10 bits Hence, the 24 bit address generated by CPU would have following components: Tag (10 bits) Set/Index (6 bits) Word (8 bits) Physical Address A1 = 0x 42C8A4. Converting it into binary gives: 0100 0010 11 00 1000 1010 0100 Physical Address A2 = 0x 546888. Converting it into binary gives: 0101 0100 01 10 1000 1000 1000 Physical Address A3 = 0x 6A289C. Converting it into binary gives: 0110 1010 00 10 1000 1001 1100 Physical Address A4 =0x 5E4880. Converting it into binary gives: 0101 1110 01 00 1000 1000 0000 Thus it can be observed that A2 and A3 map to same set. Also, address A1 and A4 map to same set. Tips and Tricks: The following approach should be adopted to quickly solve this question and save a lot of time:- The number of bits for tag in a K- way set associative memory can be calculated directly as: (log2 (Main memory size in Bytes) – log2 (Cache memory size in Bytes)) + log2 K Another thing is that the question is concerned only about the set number of the given addresses. So, we need not convert first two Hex digits of the given address into binary format, because they would be part of tag bits. Similarly, the last two Hex digits need not be converted into binary as they are part of Word/Offset. Only the middle two Hex digit needs to be converted into binary. And then the 6 LSBs can be compared to check if they represent the same set or not.